The present invention generally relates to step-up circuits, and more particularly, step-up circuits that perform a charge pump operation.
To drive an LCD panel, for example, a voltage of 12-18V may be required when the duty is {fraction (1/100)}. However, since the power supply voltage of recent Integrated Circuits (xe2x80x9cICsxe2x80x9d) is a DC voltage of 1.8-3.6V, the power supply voltage must be stepped up by a step-up circuit to drive a LCD panel with such voltages.
FIG. 9(a) shows a state in which a step-up circuit is not operating. As indicated in FIG. 9(b), when clock signals V1-V4 are supplied to gates of transistors Q1-Q4, respectively, the step-up circuit starts its operation, and steps up a voltage between a first power supply potential VDD and a second power supply potential VSS to output an output potential VOUT.
In FIG. 9(b), the transistors Q2 and Q4 are turned on, a current flows in a direction indicated by an arrow, and a charge is supplied to a flying capacitor C1. In this instance, the power supply potential VDD drops momentarily. If the same power supply potential VDD is also used in other circuits that are sensitive to changes in the power supply potential, these circuits may possibly malfunction. Furthermore, when a plurality of step-up circuits like the one indicated in FIGS. 9(a) and 9(b) are used, a change in the power supply potential VDD tends to become greater.
Accordingly, there is a need for step-up circuits that can reduce and/or possibly eliminate changes in the power supply potential upon starting a step-up circuit.
A step-up circuit in accordance with a first aspect of the present invention is equipped with a step-up clock signal generation device that generates a clock signal to be used for voltage step-up, a plurality of step-up stages for successively stepping up a power supply voltage based on the clock signal, and a control device that controls, after starting an operation, the clock signal generated by the step-up clock signal generation device to be supplied to the plurality of step-up stages at different timings.
In some embodiments, the step-up clock signal generation device may generate a clock signal to be used for voltage step-up based on a clock signal applied, and the control device may include a counter that counts the clock signal applied to the step-up clock signal generation circuit, and a plurality of output control circuits that respectively supply, based on different output values of the counter, the clock signal generated by the step-up clock signal generation circuit to the plurality of step-up stages.
Alternatively, in other embodiments, the control device may include a counter that counts pulse signals applied, and a plurality of output control circuits that respectively supply, based on different output values of the counter, the clock signal generated by the step-up clock signal generation circuit to the plurality of step-up stages.
A step-up circuit in accordance with a second aspect of the present invention may be equipped with a step-up clock signal generation circuit that generates a clock signal to be used for voltage step-up, a plurality of step-up stages that successively step up a power supply voltage based on the clock signal, and a control device that, after a start of operation, activates the plurality of step-up stages at different timings.
In some embodiments, the step-up clock signal generation device may generate a clock signal to be used for voltage step-up based on a clock signal applied. The control device may include a counter that counts the clock signal applied to the step-up clock signal generation circuit. The plurality of output stages can be activated based on different output values of the counter.
Alternatively, the control device may include a counter that counts pulse signals applied. The plurality of step-up stages can be activated based on different output values of the counter.
A step-up circuit in accordance with a third aspect of the present invention is equipped with a step-up clock signal generation device that generates a clock signal to be used for voltage step-up, at least one step-up stage that steps up a power supply voltage based on the clock signal, and a control device that, after starting an operation, changes a frequency of the clock signal to be supplied to the step-up stage from a value lower than a normal value to the normal value.
In some embodiments, the control device may include a plurality of frequency-divider circuits that frequency-divide the clock signal generated by the step-up clock signal generation device, and respectively output a plurality of frequency-divided clock signals having different frequency division ratios, a selector circuit that selects, based on a control signal, one of the clock signal and the plurality of frequency-divided clock signals, and a counter that counts the clock signal selected by the selector circuit to thereby generate the control signal. The step-up stage may step up the power supply voltage based on the clock signal selected by the selector circuit.
Alternatively, the control device may include a plurality of frequency-divider circuits that frequency-divide a clock signal applied, and respectively output a plurality of frequency-divided clock signals having different frequency division ratios, a selector circuit that selects, based on a control signal, one of the clock signal and the plurality of frequency-divided clock signals, and a counter that counts the clock signal selected by the selector circuit to thereby generate the control signal. The step-up clock signal generation circuit may generate, based on the clock signal selected by the selector circuit, a clock signal to be used for voltage step-up.
In other embodiments, the control device may include a plurality of frequency-divider circuits that frequency-divide a clock signal applied, and respectively output a plurality of frequency-divided clock signals having different frequency division ratios, a counter that counts pulse signals applied, and a selector circuit that selects, based on an output value of the counter, one of the clock signal and the plurality of frequency-divided clock signals, and the step-up clock signal generation circuit may generate, based on the clock signal selected by the selector circuit, a clock signal to be used for voltage step-up.
In accordance with the first aspect of the present invention, after an operation is started, the clock signals generated by the step-up clock signal generation device are supplied to a plurality of step-up stages at different timings, such that changes in the power supply potential can be reduced at the time of starting an operation of the step-up circuit.
Also, in accordance with the second aspect of the present invention, after an operation is started, a plurality of step-up stages are activated at different timings, such that changes in the power supply potential can be reduced at the time of starting an operation of the step-up circuit.
Furthermore, in accordance with the third aspect of the present invention, after an operation is started, the frequency of a clock signal to be supplied to a plurality of step-up stages is changed from a value lower than a normal value to the normal value, such that changes in the power supply potential can be reduced at the time of starting an operation of the step-up circuit.